Memory cells of dynamic random access memories (DRAMs) in each case include a cell capacitor or storage capacitor for storing an electric charge, which characterizes the information content of the memory cell, and a cell transistor or select transistor for selectively addressing the memory cell.
The select transistors of the memory cells are provided as field-effect transistors each having an active area and a gate electrode. The active area includes two source/drain regions and a channel region. The source/drain regions are usually formed as n-doped regions in each case below a substrate surface in a semiconductor substrate. The channel region is provided as an undoped or lightly p-doped region in the semiconductor substrate and separates the two source/drain regions from one another. The channel regions of the select transistors are connected to a cohesive region of the same conductivity in the semiconductor substrate.
The gate electrodes of the select transistors are arranged above the respective channel region and are insulated from the semiconductor substrate by a gate dielectric which lies on the substrate surface of the semiconductor substrate. The gate electrodes of a plurality of memory cells arranged next to one another are formed as sections of addressing or word lines.
When the memory cell is operating, the formation of a conductive channel between the two source/drain regions by the channel region is controlled by a suitable potential at the gate electrode.
In the ON state of the select transistor, a storage electrode of the storage capacitor is connected to a data line or bit line. In the unaddressed state of the memory cell, the storage electrode is insulated from the bit line.
In the case of trench memory cells, the storage capacitors are formed as trench capacitors oriented at hole trenches which have been introduced into the semiconductor substrate from the substrate surface. The filling of the hole trench forms an inner or storage electrode. The opposite or outer electrode is formed by a doped region in a section of the semiconductor substrate which surrounds a lower section of the hole trench. In an upper section of the hole trench, formed between the substrate surface and the lower section, the filling of the hole trench is insulated from the semiconductor substrate by a collar insulator, and in the lower section opposite the outer electrode, the filling of the hole trench is insulated from the semiconductor substrate by a capacitor dielectric provided at the wall of the hole trench.
The connection of the storage electrode of the trench capacitor to the first source/drain region or the node junction of the associated select transistor, in concepts which are suitable for production lines, is usually effected as a buried strap via an electrically conductive interface (buried strap window) between the generally polycrystalline filling of the hole trench and the adjoining single-crystal semiconductor substrate below the substrate surface.
In the case of stack memory cells, the storage capacitor is provided as a stacked or stack capacitor outside the semiconductor substrate above the word lines. The connection of the storage electrodes of the stack capacitors to the respectively associated first source/drain region or node junction of the select transistor and the connection of bit lines provided above the word lines to the respective second source/drain region are effected in the same way via identical contact structures which pass between the word lines to the semiconductor substrate.
The costs per memory cell are being lowered by an ongoing reduction in the planar dimensions of the memory cells and the resulting higher yield of storage bits per wafer. To partially compensate for the associated loss of capacitance in the storage capacitors, the vertical dimensions of these capacitors are increased above the semiconductor substrate and/or into the depth of the semiconductor substrate relative to the planar dimensions. The aspect ratio of depth to width of trench structures that are to be processed is increased, making processing more difficult.
In cell concepts that provide a combination of stack and trench memory cells, the storage capacitors are realized on two levels. Based on the planar dimensions, there is consequently in principle twice the space available for forming the individual storage capacitors compared to cell concepts which provide exclusively stack or trench memory cells.
A DRAM twin cell is described in U.S. Pat. No. 6,184,548 B1 (Chi et al.). The twin cell includes two cell transistors which are addressed via a common addressing line. A trench capacitor is connected to a first bit line via the first cell transistor, and a stack capacitor is connected to a second bit line via the second cell transistor. The trench capacitor is formed between the two select transistors of the twin cell. On account of the fact that half the storage capacitors are formed above the substrate surface and the other half of the storage capacitors are formed below the substrate surface, it is possible to correspondingly increase the planar dimensions of all the storage capacitors.
One drawback of the concept described is the need for additional insulator structures on all sides of the twin cells.
U.S. Pat. No. 6,493,253 (Hofmeister) describes a DRAM memory cell in which the capacitance of a trench capacitor is increased by a stack capacitor connected in parallel with the trench capacitor.
A further memory cell concept with trench and stack capacitors is disclosed by U.S. Pat. No. 5,942,777 (Chang). The memory cell array in each case includes pairs of trench memory cells and pairs of stack memory cells. The memory cells are connected by means of parallel bit lines and parallel word lines. The trench memory cells are in each case arranged in pairs and formed along the bit lines. Each pair of trench memory cell runs via a common bit contact to the respectively associated bit line. Stack memory cells are likewise organized in pairs, oriented orthogonally with respect to the trench cell pairs and run in pairs onto the common bit contact. The trench memory cells are addressed via word lines running orthogonally with respect to the bit lines. The stack memory cells are addressed via word lines that are formed parallel to the bit lines and arranged alternately with the bit lines. The planar dimensions of the select transistors of trench and stack memory cells are substantially independent of one another in terms of process engineering.
Linking of trench and stack technologies that are currently sufficiently developed to be used in production leads to combined memory cells with a buried semiconductor connection between the trench capacitor and the trench select transistor, as well as a bit-contact-type connection between the stack capacitor and the stack select transistor. The type of connection to the node junction of the respective select transistor influences the characteristics of the associated memory cell. The properties of the trench memory cells and of the stack memory cells can only be matched to one another in a complex and expensive way.